VHDL Modeling of Convolutional Interleaver- Deinterleaver for Efficient FPGA Implementation

Interleaving along with error correction coding is an effective way to deal with different types of error in digital data communication. Error burst due to multipath fading and from other sources in a digital channel may be effectively combated by interleaving technique. In this paper an efficient technique to model convolutional interleaver using a hardware description language is proposed and implemented on field programmable gate array (FPGA) chip. Our technique utilizes embedded shift register of FPGA chip to implement incremental shift register in the interleaver. Software simulation of the model is presented. The proposed technique reduces consumption of FPGA resources to a large extent compared to conventional implementation technique using flip-flop. This implies lower power consumption and reduced delay in the interconnection network of the FPGA. This technique is also efficient in reducing wastage of memory compared to memory based implementation technique for digital audio broadcasting (DAB) application.